1. Field of the Invention
The present invention relates in general to a method of manufacturing a semiconductor device and, more particularly, to a method which is adapted to produce a composite device of a transistor and other elements.
2. Description of Related Art
In the conventional bipolar transistor manufacturing methods previously known, it has generally been customary to adopt procedures which comprise the steps of first forming a buried layer and an N-type epitaxial layer, then double-diffusing impurities of first and second conduction types selectively into an active region which is surrounded by isolated inter-element regions, thereby forming a base region and an emitter region.
The latest developments of process technology have given rise to requirements for realizing higher integration densities and higher operation speeds of the elements. For the purpose of meeting such requirements, it is usual to employ a polycrystal silicon washed emitter (hereinafter referred simply to as poly-washed emitter) structure. The use of such poly-washed emitter structure makes it possible to form a self-matched emitter region. Such structure contributes to the reduction in size of an emitter opening (which results in the reduction of the cell size), and also to the decrease of base broadening resistance Rbb' which consequently results in advantages which allow obtaining higher integration density and higher operation speeds of the elements.
FIGS. 3A-3F illustrate a more specific description of a method for the manufacture of a bipolar transistor which has a poly-washed emitter structure. First, as shown in FIG. 3-A, an N-type buried layer 32 and an N-type epitaxial layer 33 are formed on a P-type semiconductor substrate 31. Then a P-type isolated inter-element region 34 and another isolated inter-element region 35 composed of a thick thermal oxide layer are formed. Then a P-type impurity is selectively ion-implanted into an active region 36 which is surrounded by isolated inter-element regions 34 and 35 to thereby form a base region 37. An N-type impurity is ion-implanted into a portion where a collector contact is to be formed, thereby forming a collector lead region 38 which extends up to the buried layer 32. Subsequently a silicon dioxide film 39 is formed by CVD (chemical vapor deposition) or the like on the entire surface inclusive of the active region 36.
Thereafter, as shown in FIG. 3-B, the silicon dioxide film 39 is selectively etched through a resist mask 40 so as to form open windows 39e and 39c in the portions corresponding to the emitter region (which will serve also as an emitter contact) and the collector contact of the active region 3 6.
In the next step, as shown in FIG. 3-C, the resist mask 40 on the silicon dioxide film 39 is removed, and a polycrystal silicon layer 41 is formed on the silicon dioxide film 39 including the windows 39e and 39c. Thereafter an N-type impurity (e.g. As.sup.+) is ion-implanted into the polycrystal silicon layer 41, and a heat treatment is performed so as to diffuse the N-type impurity from the polycrystal silicon layer 41, thereby forming an emitter region 42e (which serves also as an emitter contact) and a collector contact 42c (which is represented by a broken line) in a self-matched state.
Subsequently, as shown in FIG. 3-D, the polycrystal silicon layer 41 is patterned.
In the next step, as shown in FIG. 3-E, a resist mask 43 is formed on the polycrystal silicon layer 41 and the silicon dioxide film 39, and then the silicon dioxide film 39 is etched through the resist mask 43 so as to form a window 39b at a position which corresponds to the base contact.
Subsequently, as shown in FIG. 3-F, an aluminum layer is formed on the entire surface after removal of the resist film 43, and such aluminum layer is patterned so as to form an emitter electrode 44e which is connected to the emitter region 42e through the polycrystal silicon layer 41, a base electrode 44b which is connected to the base region 37, and a collector electrode 44c which is connected to the collector contact 42c through the polycrystal silicon layer 41, and a desired bipolar transistor is thus produced.
However, according to the conventional method of manufacturing a bipolar transistor, the step of forming the windows 39e and 39c which are opposed to the emitter region 42e and the collector contact 42c is different from the step of forming the window 39b which is opposed to the base region 37, and thus a total of two resist masks (denoted by 40 and 43 in FIG. 3) are required for opening the windows. Particularly when forming a composite device of a transistor, a resistor, a capacitor and so forth, a window opening resist mask is required for forming each element and consequently this makes the window opening step complicated. Also for ion implantation, generally resist masks are required in conformity with the individual conduction types of the impurities, so that a multiplicity of resist masks are required for forming elements and these are additional to the aforementioned window-opening resist masks, and thus the manufacture of a composite device becomes complicated.
It has been recently observed that, as faster operation and higher frequency band in the linear technical field for public use (including analog IC&lt;analog LSI, etc.) have been developed that there are some devices which utilize the poly-washed emitter type in the general linear process as well. For the purpose of improving the noise and frequency characteristics, it is desired that a MIS capacitor be employed as a filter. However, since a composite device is produced by a combination of different steps for the individual elements as described, the steps become complicated and harmful influences occur due to heat treatment and so forth when forming other elements which consequently causes a deterioration in the precision of the capacitance control, thereby causing additional difficulties during manufacture (including the simultaneous production of a MIS capacitor for a transistor of a poly-washed emitter structure).